Forbes reports on FPGA cluster computing

Andy Greenberg at Forbes Magazine has featured FPGA cluster computing in an article titled A Compact Code-Breaking Powerhouse. It’s a good article, check it out.


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Partial reconfiguration – it’s about time

Altera today announced that its next-generation, 28nm devices will support partial reconfiguration. This means that Altera FPGA users will now be able to update small portions of an FPGA device, rather than having to re-synthesize, re-map and reprogram the entire device every time the application changes.

Xilinx has supported this feature for quite a few years, but has never made it a mainstream, supported feature of their ISE Design Suite development tools. However, in a recent email update to its customers, Xilinx announced with almost no fanfare that, in version 12 of the Xilinx tools, this important capability would finally be given its proper status as a supported feature. Perhaps the marketing department at Xilinx heard rumors coming from the other side of San Jose?

Corporate intrigue aside, this is an important piece of news. Why? Because software application developers first investigating FPGAs are surprised – even shocked – to learn how long the iteration times are for programming and debugging FPGA applications. And the larger the FPGA is, the worse the problem becomes.

For most software developers, being faced with the equivalent of a two, three, or even eight hour iteration time for compile-link-test is completely unacceptable, no matter how much potential increase in performance there may be.

And if, at the end of that long iteration time all the programmer has is a non-working, difficult-to-debug bitmap and a thousand-lines long report filled with hardware-esque warning messages? Then forget it. They might as well go use GPUs and CUDA.

So, why has it taken so long for this seemingly obvious feature to become mainstream? One can only assume that Xilinx and Altera management, their chip architects, and perhaps even their tools developers are hardware engineers first, and software engineers second. Perhaps they can only think of their devices as the poor-man’s ASIC. And their tools as a poor-man’s EDA.

Reliable, vendor-supported partial reconfiguration, including dynamic run-time reconfiguration, has the potential to solve so many problems for software application developers, and to broaden the market for FPGAs.


Partial reconfiguration allows developers to iteratively recompile, re-synthesize, re-map and re-test a specific portion of the FPGA in just a few minutes, rather than a few hours. This in itself is a huge benefit. Instead of having to set up elaborate, hardware-oriented simulations to verify correct behavior before hitting that compile button, you can just try it out, again and again, in the same way you would when developing software. Indeed, this method of design was predominant for FPGAs in the 1980s and early 1990s. But as device densities have grown, iterative design-and-test methods have become impractical. That was good for the hardware simulator business, but bad for software developers.

Run-time reconfiguration allows certain parts of the FPGA to remain intact and functioning, for example the I/O processing, while other parts are being updated on-the-fly. Need to change the filtering of a video signal to respond to a change in resolution? Wham, it’s done, and so fast the viewer doesn’t even see a flicker. Want to change the FPGA’s function without causing a system reboot? How about leaving the PCIe endpoint alone and just changing the core algorithm?

Dynamic reconfiguration can increase the effective size of an FPGA. Loading of partial bitmaps at run-time allows the capacity of these devices to grow in the dimension of time. If you don’t need all the hardware capabilities you have programmed into your FPGA all the time, then use dynamic reconfiguration to swap hardware modules in and out as needed. Use reconfiguration to do more, with less.

Partial reconfiguration opens up new FPGA markets. Using partial reconfiguration, the vendors of FPGA-based platforms for specific types of applications – for financial transaction processing and automated trading, for example – could provide a “minimally programmable embedded system” in which most of the FPGA logic is pre-designed, pre-optimized and locked down, while a small portion in the middle is left available for end-user customization. This potentially opens up whole new application domains that were previously not available for FPGAs; applications in which the platform vendor and the end user both have unique domain knowledge, and have their own critical IP to protect.

Again, these capabilities are not really new; the Xilinx partial reconfiguration features have been used successfully, for years, in domains such as software-defined radio. What’s changing is that partial reconfiguration is finally becoming officially supported. With uncertainties about its future and its supportability reduced, software and platform vendors will now begin using these features to enable new programming, debugging and operating features into their own products.

It’s about time.


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Cracking the Genomics Code

This week I was in San Diego attending the International Plant and Animal Genome Conference. PAG is a conference that brings together academic and commercial researchers and product vendors, with a particular emphasis on agricultural applications. (One of the first signs I saw when entering the lobby was a sign directing attendees to a “Sheep and Cattle” workshop. I wondered who would be cleaning the hotel carpets.)

In an earlier post, Please pass the dot plots, I described how Greg Edvenson at Pico Computing used an FPGA cluster and C-to-FPGA methods to demonstrate acceleration of a DNA sequence comparison algorithm. The quick success of that project was reason enough for us to attend PAG and learn more about the computing problems in genomics. Where are acceleration solutions needed?

It’s clear there are problems aplenty to be solved. As one researcher said to us, “The amount of raw data being generated by DNA sequencers each month is outpacing Moore’s Law by a wide margin.” He went on to describe how his group routinely undocks and hand-carries their hard drives down the hall because the time required to move the generated sequencing data across their network is too long. Solutions are needed for accelerating data storage throughput, and for the actual computations to do such things as assemble whole genomes from the small chunks of scrambled DNA that currently emerge from sequencing machines.

Why all the data? The human genome is about 2.91 billion base pairs in length*, and it’s not the longest genome out there, not even close. We have more base pairs than a pufferfish (365 million base pairs) but far less than a lungfish (130 billion base pairs).

Evolution is a curious crucible.

Sequencing technologies have advanced quickly. Machines and software offered by Illumina, Life Technologies, Roche and others can generate enormous amounts of genetic data. The bottleneck at present is in assembling all that data – like a billion-part jigzaw puzzle thrown to the floor – into a meaningful, searchable DNA sequence. The methods of doing this assembly, using algorithms such as ABySS and Velvet, may require parallelizing the problem across many CPUs, and using large amounts of intermediate memory – potentially terabytes of it.

If you are a researcher trying to figure out, for example, how to increase crop yields in sub-Saharan Africa, then you might be very interested in knowing how to breed a more pest-resistant and productive variety of barley (5 billion base pairs) or wheat (over 16 billion base pairs).

And if you’re Dupont or Monsanto, you may want to actually create and patent such a grain to have a competitive advantage.

To figure out such things, you may want to perform sequence comparisons of other species that appear to have the characteristics you are interested, and find the relevant genetic variances. You won’t have a chance of doing this unless you can sequence many varieties and perform detailed analysis of what you see. This takes lots of computing time and bags of money.

And so the gemonics industry looks for faster solutions for cracking the codes of life. The solutions involve cluster and cloud computing, GPUs and FPGAs, and perhaps exotic hybrid computing platforms to come.

*A “base pair” is two complementary nucleotides in a DNA strand, connected by a hydrogen bond. There are four kinds of nucleotides that make up these base pairs: adenine, thymine, guanine and cytosine. In the human genome only a small fraction of these base pairs are actually representing genes. It seems our bodies are mostly “junk DNA“, perhaps proving that we are what we eat.

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Time to throw away our GSM phones?

The mobile phone industry is in full PR battle mode this week with the news that a computer scientist has successfully cracked the A5/1 encryption code that secures GSM mobile phone calls. In theory this means that anyone having access to appropriate snooping hardware and software, estimated by the researcher to cost under $30,000, can listen in on GSM phone calls by intercepting and decoding radio signals.

Last week at the Chaos Communication Congress in Berlin, Dr. Karsten Nohl announced that his team, a group of hackers working collaboratively to create a distributed computing cluster, had cracked the encryption code by creating an enormous, 2-terabyte “rainbow table” of hash values. In simplistic terms, the rainbow table provides a cracking program with a reverse-lookup scheme that can quickly decrypt the wireless voice data.

I’ll leave aside any prediction of who might want to use this kind of cracking technology, and where they might want to do it. In the United States GSM is used for only a fraction of communications, most notably by AT&T and T-Mobile.

GSM dominates worldwide, however, carrying the overwhelming majority of phone calls. (And if you are an iPhone user like I am, you should know that AT&T most probably sends your voice via the 2G GSM standard using A5/1 encryption, even though you are paying for presumably more secure 3G service. And if you think your iPhone data is secure… read this.)

From a computing perspective, what’s interesting about this project is that it required two types of computational acceleration. The first computing problem was the creation of the rainbow tables. This only needed to be done one time, but represented a massive computing problem. Nohl estimated that to generate these tables using a single traditional PC or server would have required many years to complete. To make this problem practical, Nohl and his collaborators set up a distributed computing system similar to the SETI@Home project in which the spare computing cycles from many different computers on the Internet were harnessed to calculate the needed tables. In some of the computers GPUs were also used to accelerate the problem, which was completed in three months of calendar time.

The second computing problem occurs at the point of decryption, in whatever server or laptop PC is being used to snoop and crack the wireless signal. That problem is also computationally intensive, but with ready access to the 2-Terabyte rainbow tables the crack can be performed in minutes, or seconds if GPU and/or FPGA accelerators are added into the mix.

During his talk, Nohl stated that a person (or agency?) wanting to eavesdrop on GSM calls would currently need to spend around $100,000 on hardware in order to crack an A5/1 encrypted call in one second or less. And the hardware to use? A cluster of 64 or more FPGAs. For less money and slower cracking times (still under a minute, and under $30,000) a smaller number of FPGAs or GPUs would do the job just fine.

Slides from Nohl’s talk are here.

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Trash-talking CUDA

Found lurking on, in an interview with Steve Wallach of Convey Computer:

…I call programs that don’t take into consideration legacy systems and that are obscenely difficult to integrate, “pornographic” programs — you can’t always describe them exactly, but you know them when you see them. In 1984, I converted a FORTRAN program from CDC to ANSI FORTRAN to see what they were doing and it was awful. In the contemporary world, CUDA is the new pornographic programming language.

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Please pass the dot plots

In the past year there has been an increased level of skepticism regarding FPGAs as computing devices. Large amounts of ink of been spilled regarding the emergence of GPUs as general-purpose computing platforms. NVIDIA’s Tesla is racking up high benchmark scores in domains that include computational finance, scientific computing, geophysics and many others.

Nonetheless, there are certain domains in which FPGAs are clear winners over GPUs, particularly when power consumption is factored into the results. Two of these domains are crypto-analysis (code cracking) and bioinformatics.

The CHREC group at the University of Florida, and Pico Computing of Seattle, have both recently announced benchmark results for DNA sequencing algorithms. Both groups used FPGA clusters to perform massively parallel computations and to accelerate the comparing and scoring of DNA base pairs by orders of magnitude.

The Florida group, led by Dr. Alan George, implemented a Smith-Waterman sequencing algorithm on a cluster of 96 Altera high-capacity FPGA devices, using PCI Express FPGA cards supplied by GiDEL.

The Novo-G cluster used for this project consists of 16 Linux servers, each housing a quad-FPGA accelerator board from GiDEL. According to the CHREC team, Novo-G’s performance was compared with an optimized software implementation executed on a single 64-bit, 2.4GHz AMD Opteron core. A speedup of 40,849X was observed. The implication is that a bioinformatics calculation that would take days to run on a single desktop workstation or server would require just seconds to complete using the Novo-G FPGA cluster.

In Seattle, Pico Computing implemented a similar algorithm that performs sequence analysis and scoring to create a 2-dimensional figure called a dot plot. The Pico team reported that they had achieved greater than 5000X acceleration of their algorithm, using a cluster of 112 Xilinx Spartan-3 FPGA devices. The Pico cluster consumed less than 300 Watts of power, with all FPGAs fitting comfortably into a single 4U server chassis.

Perhaps more interesting about the Pico Computing project was how it was developed. Greg Edvenson of Pico used a single FPGA device during initial algorithm development. The FPGA was encapsulated in a Pico Computing E-17 card attached directly to Greg’s laptop computer via an ExpressCard interface. After the algorithm was tested and working as a single hardware process, Edvenson then scaled up and replicated the algorithm for deployment on the FPGA cluster. Greg used C-to-FPGA tools provided by Impulse Accelerated Technologies during the development of the algorithms, reducing the need to write low-level HDL code.

In summary, bioinformatics is one application domain in which FPGA acceleration offers clear and compelling benefits. And as well, there are multiple FPGA cluster approaches that can be taken to meet the needs of the application, and to meet the constraints of budget and power consumption.

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Dirty words and wardrobe malfunctions

Saving the world, one $#&^! FPGA at a time…

School system to use Algolith Profanity Cleaner and Delay System for live broadcasts

Okay, so maybe it was a slow news day when this got picked up. But digging deeper, what Algolith is offering is a reconfigurable, FPGA-based delay and filtering application for audio and video.

In their literature, Algolith is promoting the concept of One Card, One Price, More Choices. This is fundamentally what reconfigurable hardware is all about, and it makes sense for both the customer and for Algolith.

Why? Because video filtering and other broadcast video applications require hardware solutions, but don’t have static requirements. What’s needed for broadcasting, say, the Superbowl with 50 or more HD cameras, chaotic real-time action and thousands of opportunities for verbal and visual naughtiness, is probably quite different than the requirements for broadcasting a heathcare town meeting with a few unruly seniors.

How does reconfigurable hardware come in? A vendor such as Algolith can design and produce a hardware based solution, such as an HD-compatible video card, that has at its core one or more FPGAs. Some of the logic in these FPGAs is fixed and rarely updated, handling those parts of video processing that don’t change. Interfacing with video and network I/O devices, for example. Other parts of the video processing, however, are reconfigurable, allowing new types of clever delay filtering and other video gymnastics to be performed by the customer. Want to fuzz out someone’s unfortunate wardrobe problems with one mouse click, and track the offending [insert noun here] even as it moves around the scene? How about hiding all those annoying non-sponsor brand logos? Hey, somebody’s got to keep the viewers safe.

I don’t know if Algolith offers such high-zoot features in its video products, but these sorts of capabilities are certainly possible to implement in FPGAs today.

From a marketing perspective, the really attractive thing about reconfigurable hardware is the ability for a company like Algolith to become more than a hardware vendor – which is not a particularly scalable business – into a vendor of IP and services that use their reconfigurable hardware product as a platform for value-added options and reconfigurable firmware upgrades. And that’s a way $&@%*%! better business to be in.

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