Now this was a rather clever demonstration that our pals at Pico Computing had running at SC07. Take a Where’s Waldo book, point a camera at it, snap a picture and use FPGAs to do a fast pattern match and find Waldo. The results (in half a second or less) looked something like this:
The algorithm involves a pipeline of filters, performing noise reduction, image subtraction and other operations. Some of the filtering is done on a host PC, while other parts are parallelized and compiled (using the Impulse C compiler) to the FPGA co-processor for acceleration. Neat!
This past week a group of us were in Reno to attend Supercomputing 2007. (The actual name of this event is the International Conference for High Performance Computing, Networking, Storage and Analysis but nobody can remember all that.)
On Sunday the 11th I was part of a panel discussion on reconfigurable computing, then I spent the next four days manning various partner company booths including Silicon Graphics, Cray, DRC Computer, GiDEL, Pico Computing and others. This conference was a big deal for FPGA computing. Lots of good press, a number of compelling acceleration demonstrations, and a feeling that the various platforms had finally matured and were ready for larger-scale deployment. There is competition beginning to emerge between GP-GPU, Cell and FPGA-based accelerators, but the performance/power advantages of FPGAs remain compelling.
On Tuesday, just a few hours after the conference exhibits had opened, there was a loss of power that resulted in what many were soon describing as the world’s largest reboot. After all those massive compute clusters went down, the convention center was earily quiet (and dimly lit) for 15 minutes or so. Then the power returned, and the massive rebooting began. It sure would have been fun to watch the power meter spin as thousands upon thousands of high-end processors, disks, memories and network equipment came back up.