Ed put together another “way cool” demo, this one for Embedded World in Germany.
For this show, we wanted to demonstrate the use of two embedded PowerPC processors operating in concert in a single FPGA, with Impulse-generated C-language coprocessors attached to each PowerPC along with other needed soft-hardware peripherals.
Here’s a block diagram of the demonstration, featuring Ed’s smiling and emboss-filtered face (sorry Ed!):
All of this stuff is running on a single FPGA device, a Xilinx Virtex-4 FX60. There are two PowerPCs provided in the FX60 device. As the block diagram shows, one of the PowerPCs is being dedicated for processing images that come in from a network JPEG camera. There is no operating system running on this dedicated PowerPC, just a single application that reads data from the hardware TEMAC interface and performs JPEG decoding of the streaming video. To speed up this decoding, a hardware accelerator has been added as a peripheral to perform an inverse discrete cosine transform (IDCT) operation. This accelerator was written and C and compiled by our tools into a hardware module/peripheral.
After decoding of the image frames, the video data (now in RGB format) is streamed directly to the second PowerPC, again using Impulse-generated hardware modules. One of these Impulse C hardware modules is a configurable image filter that allows such things as emboss, edge detect, blur, color conversion, etc. The processor-to-processor interfaces in the FPGA are implemented using a special Xilinx Virtex-4 feature called the Auxiliary Processing Unit, or APU. Our tools automatically generate the needed APU interfaces for Xilinx, making such connections relatively easy to create.
There is more fun happening in the second PowerPC. This processor runs the VxWorks operating system and an embedded web server. This means that the images being captured and filtered frame-by-frame from the camera can either be displayed on a TFT display (as shown) or be served up via a webpage.
This is a great example of how single-chip, multiple-processor embedded applications can be created using tools like ours, and using the latest FPGA devices. You can bet we’ll be seeing more examples like this in the future, possibly including a large number of embedded processors to create single-chip, accelerated computing clusters.