Tag Archives: image processing

Slaughterhouse Virtex-5?

FPGAs are appearing in some, ah, interesting places. Read about Automated Meat Processing in Vision Systems Magazine.

Embedded 3-D machine-vision system guides robotic cutting of beef carcasses

The stereo vision system used in this industrial-sized nail clipper is pretty cool. The manufacturer describes it this way:

TYZX’ DeepSea G2 Stereo Vision System is a small embedded camera with low power requirements that delivers high performance visual analysis (up to 60 fps) in variable lighting conditions. Designed for widespread deployment in applications such as security and navigation, the G2 provides real-time 3D vision processing without the use of workstations…

The DeepSea G2 system is based around Xilinx FPGAs that perform image rectification, 2D and 3D quantization and other compute-intensive tasks. In a technical white paper, the system designers describe how the FPGA is combined with an ADI Blackfin processor and a custom ASIC to strike the right balance between performance and flexibility. One interesting tidbit is found in the following table, where the first and second generation products are described:

Resource table

Notice that the Pentium III processor that did much of the heavy lifting in their first-generation product completely disappears in the second generation. This example points again to the need for tools and design methods that support partitioning between many different types of processing elements.


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Filtered backprojection and FPGAs

David Pointer at SRC Computer on the use of FPGAs for Filtered Backprojection (FBP), a critical component of medical imaging and other domains:

“Projecting” images in radar and medical applications

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Spacecraft image processing gets a boost

Here’s a cool article by one of our users, Paula Pingree at Jet Propulsion Laboratories:

Developing FPGA Coprocessors for Performance-Accelerated Spacecraft Image Processing

(Gosh, this stuff really is rocket science.)

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Where’s Waldo?

Now this was a rather clever demonstration that our pals at Pico Computing had running at SC07. Take a Where’s Waldo book, point a camera at it, snap a picture and use FPGAs to do a fast pattern match and find Waldo. The results (in half a second or less) looked something like this:

Finding Waldo

The algorithm involves a pipeline of filters, performing noise reduction, image subtraction and other operations. Some of the filtering is done on a host PC, while other parts are parallelized and compiled (using the Impulse C compiler) to the FPGA co-processor for acceleration. Neat!

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