Tag Archives: nanowire

HP dabbling in future FPGA technology?

This article on CNET, Can HP fool Moore’s Law?, describes research at HP into a very different FPGA interconnect strategy based on nanowires:

As the article points out, transistor interconnects dominate the area of large-scale FPGAs, leading to lower levels of power efficiency and larger required area and costs than might otherwise be possible. The flexibility of interconnections is one of the main benefits of an FPGA, but this flexibility brings with it compromises. The HP approach looks promising because, as the article says:

By removing the traditional interconnects [and replacing them with much more compact nanowire crossbars], the size of a given chip would naturally and drastically shrink. Performance would increase, but the chips could still be made out of traditional transistors. Cost would ideally decline because the advance wouldn’t require investing billions of dollars in new semiconductor manufacturing equipment. Power consumption would likely fall, at the same time.

The key to this is that the nanowire crossbar approach does not require a fundamentally different IC technology, or a change to the basic architecture of the FPGA logic blocks. A great example of making fundamental, yet incremental improvements to an existing technology.

This will be something worth watching.

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