Tag Archives: power

A new low-power FPGA?

The power efficiency of FPGAs is either very good, or very bad, depending on who you’re talking to. If you are comparing math performance, meaning the number of integer or floating point operations performed per watt of power, then FPGAs look pretty good when placed side-by-side against a traditional processor or DSP. This is because the FPGA has less overhead; more of the transistors can be configured as parallel structures to do the real work of processing data and computing results. FPGAs can do the same work with fewer clock cycles, resulting in lower power consumption.

If, however, you are looking at low-power portable products such as a mobile phones and games, FPGAs are not even contenders. They have a reputation as power hogs. This is because FPGAs are dominated by interconnect and have flexible, application-independent structures. It is not possible, at least not for real applications, to make use of all the transistors in an FPGA. There is leakage, and there is static power needed because of the SRAM architecture of the most common devices. And so power is wasted.

Both Xilinx and Altera have low-power FPGA families (Spartan and Cyclone, respectively) and Actel devices are also power misers. But these devices still consume too much power for use in mobile devices.

So the news that startup SiliconBlue Technologies has a new and much lower power FPGA device is notable. Their devices are small (akin to complex PLDs) but quite FPGA-like in their design.

I’m not much of an expert on FPGA process technologies, but if SiliconBlue can actually get traction in mobile devices and scale these devices up to tackle more complex algorithms… then that could be an important step for reconfigurable embedded computing.

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